1. Field of the Invention
The present invention pertains to communications systems, and particularly to communications systems which employ ATM technology.
2. Related Art and Other Considerations
Asynchronous Transfer Mode (ATM) is becoming increasingly used in communication networks. ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and have a fixed size.
As shown in FIG. 1, an ATM cell consists of 53 octets, five of which form a header and forty eight of which constitute a xe2x80x9cpayloadxe2x80x9d or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual path is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
Between termination points of an ATM network a plurality of nodes are typically situated, such as switching nodes having ports which are connected together by physical transmission paths or links. The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially functions like a cross-connect between ports of the switch. Paths internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a cells ultimately to travel from an ingress side of the switch to an egress side of the switch.
A protocol reference model has been developed for illustrating layering of ATM. The protocol reference model layers include (from lower to higher layers) a physical layer (including both a physical medium sublayer and a transmission convergence sublayer), an ATM layer, and an ATM adaptation layer (AAL), and higher layers. The basic purpose of the AAL layer is to isolate the higher layers from specific characteristics of the ATM layer by mapping the higher-layer protocol data units (PDU) into the information field of the ATM cell and vise versa. There are several differing AAL types or categories, including AAL0, AAL1, AAL2, AAL3/4, and AAL5.
AAL2 is a standard defined by ITU recommendation I.363.2. An AAL2 packet is shown in FIG. 2 as comprising a three octet packet header, as well as a packet payload. The AAL2 packet header includes an eight bit channel identifier (CID), a six bit length indicator (LI), a five bit User-to-User indicator (UUI), and five bits of header error control (HEC). The AAL2 packet payload, which carries user data, can vary from one to forty-five octets
FIG. 3 shows how plural AAL2 packets can be inserted into a standard ATM cell. In particular, FIG. 3 shows a first ATM cell 201 and a second ATM cell 202. Each ATM cell 20 has a header 22 (e.g., cell 201 has header 221 and cell 202 has header 222). The payload of the ATM cells 20 begin with a start field 24 (e.g., cell 201 has start field 241 and cell 202 has start field 242). After each start field 24, the ATM cell payload contains AAL2 packets. For example, the payload of ATM cell 201 contains AAL2 packets 261 and 262 in their entirety, as well as a portion of AAL2 packet 263. The payload of cell 202 contains the rest of AAL2 packet 263, and AAL2 packets 264 and 265 in their entirety. In addition, the payload of cell 202 has padding 28.
The start field 24, shown in FIG. 4, facilitates one AAL2 packet bridging two ATM cells. Start field 24 includes a six bit offset field (OSF), a one bit sequence number (SN), and one parity bit (P). The six bit offset field (OSF) contains a value, represented by offset displacement 29 in FIG. 3, indicative of the octet in the payload whereat the first full AAL2 packet begins. For ATM cell 221, the value of the offset field (OSF) is one, since AAL2 packet starts just after start field 241. For ATM cell 222, the value of the offset field (OSF) is the sum of one (in view of start field 241) and the number of octets of AAL2 packet 263 protruding into cell 222.
In an ATM based telecommunications system where different quality of service classes are supported, some connections are more delay sensitive than others. In order to cater to these differing sensitivities, advanced queue management is required. As used herein, advanced queue management involves handling ATM cells of differing priority. Such advance queue management can include specific traffic management per ATM-VCC with weighted fair queuing, early packet discharge, available bit rate (ABR) accommodation, and shaping of outgoing traffic according to a traffic contract, for example. Handling of ATM traffic management is specified in the ITU I.371 Recommendation or in ATM-FORUM Traffic Management Specification 4.0.
High cost ATM switching nodes normally have advanced queue management, to a certain degree, at every output. In this regard, a typical ATM switching node the ATM switch core has a plurality of switch ports. Each utilized switch port generally has a circuit board connected thereto, with the circuit board having one or more functional units provided thereon. Some such circuit boards function as extension terminals (ETs) for interfacing the switching node with other nodes of the ATM network. Each extension terminal (ET) typically has an ingress side for handling cells received on an incoming link from another node, as well as an egress side for handling cells being sent out on an outgoing link to that other node.
In a high cost ATM switching node, either or both the ingress and egress side of an extension terminal (ET) can have some advanced queuing arrangement for the queuing of cells. For example, in an arrangement known as an input queued switch, the ingress side can have one or more buffers for queuing incoming ATM cells destined for the switch core, with a switch or selector for selecting among the buffers to obtain ATM cells for transmission to the switch core. Similarly, in an output queue switch, plural buffers can be provided on the egress side, along with a switch or selector for obtaining ATM cells from the buffers for transmission on the outgoing link. In addition to advanced queue management provided on boards such as extension terminals (ETs), queuing management can also be provided internally in the switch core in a technique known a shared queue switching. Further, combinations of both input queued switching, output queued switching, and shared queue switching are known.
Advanced queue management seeks, among other things, to control the outputs when congestion occurs in case of a temporary or permanent overload. Simple low cost ATM switches may not have advanced queue management, but instead only simple FIFO structures. Typically a low cost switch cannot, at overload, separate real time high priority traffic from not real time low priority traffic.
From a network perspective, not every switching node necessarily needs to have advanced queue management. In most cases, only a few switch outputs require advance queue handling. For other outputs overloads do not occur (since on those outputs total control of traffic is provided or al traffic has the same priority). To pay the cost for advanced queue management at all outputs of an ATM switch when only a few outputs require such is not cost effective.
Even in situations requiring advanced queue management for each output, the degree of management may vary and therefore need not be rigid. Such is especially the case since ATM quality of service handling has not been definitively defined and is not matured, i.e., new services with differing quality of service requirements may appear in the future. Such may particularly be the case in the fields of cellular telecommunications and certain internet traffic.
What is needed therefore, and an object of this invention, is a flexible and economical advanced queue management technique.
An ATM switching node has a queuing resource connected to an ATM switch core. The queuing resource provides centralized queuing for ATM cells destined for routing through the ATM switch core to plural output links. Preferably the queuing resource is provided on one or more boards connected to a port(s) of the ATM switch core, the ATM switch core also having plural terminal boards connected between plural ones of its other ports and respective ones of the plural output links. Advantageously, the centralized and selective queuing resource of the present invention obviates the necessity for queuing at each of the terminal boards.
The ATM switch core routes an ATM cell destined for any output link requiring queuing to the centralized queuing resource. ATM cells for output links not requiring queuing are not directed to the queuing resource. In one embodiment, the queuing resource forms a portion of a cell handling unit connected to the ATM switching core. In this embodiment, the ATM cells not requiring queuing are directed to the cell handling unit, but the cell handling unit detects the ATM cells not requiring queuing (e.g., a top priority cell) and enables such ATM cells to bypass the queuing resource. The top priority cells therefore short circuit the queuing resource, with the queuing resource being provided only with an indication of the existence of the top priority cell for administrative purposes. In another embodiment, the ATM switch core routes an ATM cell destined for an output link not requiring queuing directly to the output link not requiring queuing. In this direct routing embodiment, the ATM switch core may make a copy of the directly routed ATM cell (which did not require queuing) and forward the copy to the queuing resource for administrative purposes.
The queuing resource preferably comprises one or more queue servers. The queuing resource has a link multiplexer for each output link which is handled by the queuing resource. The link multiplexer has both a first stage and a second stage. The second stage comprises plural queues for storing ATM packets and a second stage multiplexer for selecting the ATM packets stored in the plural queues of the second stage for transmission to the first stage. The first stage comprises plural queues for storing ATM cells and a first stage multiplexer for selection of ATM cells including ATM cells formed of ATM packets of the second stage for discharge from the queuing resource. Preferably the ATM packets are AAL2 packets which can be multiplexed by the queuing resource to form ATM cells having the AAL2 protocol. Each of the plural queues of the first stage are assigned to a corresponding one of plural service classes of ATM cells; each of the plural queues of the second stage are assigned to a corresponding one of the same plural service classes. The plural queues of the second stage are grouped into plural queuing units, each of the queuing units being assigned to a unique VCI. Each queuing unit comprises a second stage multiplexer for selecting the ATM packets stored in the plural queues grouped therewith for transmission to the first stage.